Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model GNRFET was used to simulate performance NMOS and CMOS binary full adder. The adder evaluated in terms its average power consumption propagation delay. Three variables, namely resistance value, dimer lines channel length were manipulated impact on assessed. It observed that linear improvement delay accompanied by an exponential increase only small range values able deliver relatively reasonable trade-off between These from approximately 110 kΩ 130 kΩ. When varied 12 8 32 nm 16 nm, results showed superior as it 25.25 % at similar consumption. On other hand, choice circuit architecture required be case-by-case basis. For compute-intensive application with controlled environment, logic should chosen, while for less applications portable devices, utilised. A chosen former due 30.94 35.03 established these adders are compared MTGB based ternary gate their performance, found performed better than